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Key Specs Summary(6)
Datasheet cross-check1 matched1 enriched
- Integral Non LinearityEnriched
- 2.5LSB
- Operating Temperature
- -40℃~+85℃
- package
- CSPBGA-144(10x10)
- Resolution BitsVerified
- 16
- S N Ratio
- 92dB
- Voltage Supply
- 5V
Datasheet Extracted
Facts extracted directly from the datasheet (sourced)Pin Configuration · 144-Lead CSPBGA · 43 pins
| # | Name | Type | Function |
|---|---|---|---|
| H9 | AGND_ADC | other | Analog Power Ground Pin |
| J8 | AGND_ADC | other | Analog Power Ground Pin |
| J9 | AVDD | power in | Input Analog Power Pin. Nominally 5 V. |
| M12 | AVDD | power in | Input Analog Power Pin. Nominally 5 V. |
| M6 | AVDD | power in | Input Analog Power Pin. Nominally 5 V. |
| L7 | BYTESWAP | input | Parallel Mode Selection (8-/16-Bit). |
| L8 | OB/2C | input | Straight Binary/Binary Twos Complement. |
| M7 | WARP | input | Mode Selection. |
| L9 | IMPULSE | input | Mode Selection. |
| M8 | SER/PAR | input | Serial/Parallel Selection Input. |
| M9 | D[0:1] | output | Bit 0 and Bit 1 of the Parallel Port Data Output Bus. |
| L10 | D[0:1] | output | Bit 0 and Bit 1 of the Parallel Port Data Output Bus. |
| M10 | D[2:3] or DI/O | bidirectional | Serial master read DIVSCLK[0:1] / Digital Input Output |
| L11 | D[2:3] or DI/O | bidirectional | Serial master read DIVSCLK[0:1] / Digital Input Output |
| M11 | D[4] or EXT/INT | bidirectional | Bit 4 of Parallel Port Data Bus / Digital Select Input |
| L12 | D[5] or INVSYNC | bidirectional | Bit 5 of Parallel Port Data Bus / SYNC Selection |
| K11 | D[6] or INVSCLK | bidirectional | Bit 6 of Parallel Port Data Bus / SCLK Invert |
| K12 | D[7] or RDC/SDIN | bidirectional | Bit 7 of Parallel Port Data Bus / External data input |
| J10 | OGND | other | Input/Output Interface Digital Power Ground |
| J11 | OVDD | power in | Input/Output Interface Digital Power. Nominally 5 V or 3.3 V. |
| J12 | DVDD | power in | Digital Power. Nominally at 5 V. |
| A6 | VOUT_DAC | output | Analog Output Voltage from the DAC |
| A3 | AGND_DAC | other | Ground Reference Point for Analog Circuitry |
| C3 | AGND_DAC | other | Ground Reference Point for Analog Circuitry |
| C4 | AGND_DAC | other | Ground Reference Point for Analog Circuitry |
| A2 | VREF | input | Voltage reference input for the DAC. |
| B1 | CS_DAC | input | Active low logic input signal. Chip select. |
| E1 | SCLK | input | Clock Input. Data is clocked into the input register on the rising edge of SCLK. |
| E2 | DIN | input | Serial Data Input. Accepts 14-bit words. |
| E3 | DGND_DAC | other | Digital Ground. Ground reference for digital circuitry. |
| C6 | VDD_DAC | power in | Analog Supply Voltage, 5 V ± 10%. |
| C9 (J1) | +IN1(2) | input | Positive Input Voltage |
| A9 (G1) | –IN1(2) | input | Negative Input Voltage |
| B12 (K4) | VOUT1(2) | output | Amplifier Output Voltage |
| A11 (F3) | +VS1(2) | power in | Analog Positive Supply Voltage |
| B10 | –VS1(2) | power in | Analog Negative Supply Voltage |
| B11 | –VS1(2) | power in | Analog Negative Supply Voltage |
| G3 | +VS1(2) | power in | Analog Positive Supply Voltage |
| H3 | +VS1(2) | power in | Analog Positive Supply Voltage |
| B9 (L4) | RA1(2) | bidirectional | Resistor End Terminal |
| A8 (M4) | RB1(2) | bidirectional | Resistor Center Tap |
| D9 (L1) | RC1(2) | bidirectional | Resistor End Terminal |
| A7 (M3) | RPAD1(2) | other | Resistor Die Pad. Tie to Analog Ground. |
Source 1 ↗Extraction confidence: High
Package Info
- jedec
- MO-205AC
- package
- 144-Lead CSPBGA
Absolute Maximum Ratings
| AVDD, DVDD, OVDD Supply Voltages | 7V | |
| VDD_DAC to AGND_DAC | 6V | |
| Amplifier Supply Voltage (VS1, VS2) | 12.6V |
Recommended Operating
| Operating Temperature Range | -40 to +85°C | |
| Power Supply Sensitivity (AVDD = 5V) | ±9.5LSB |
Thermal
- unit
- °C/W
- theta ja
- 42
Ordering
- BCA
- 144-Lead CSPBGA