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주요 스펙 요약(6)
- Data Rate보강
- 20MSPS
- interface
- Logic
- Operating Supply Voltage보강
- 3V
- Operating Temperature
- -20℃~+85℃
- package
- LQFP-48(7x7)
- Pin Count보강
- 48
데이터시트 추출 정보
데이터시트에서 직접 추출한 사실 (출처 명시)핀 배치 · 48-Lead LQFP · 48 핀
| # | Name | Type | Function |
|---|---|---|---|
| 1 | NC | no connect | Internally Not Connected |
| 2 | NC | no connect | Internally Not Connected |
| 3 | D0 | output | Digital Data Output |
| 4 | D1 | output | Digital Data Output |
| 5 | D2 | output | Digital Data Output |
| 6 | D3 | output | Digital Data Output |
| 7 | D4 | output | Digital Data Output |
| 8 | D5 | output | Digital Data Output |
| 9 | D6 | output | Digital Data Output |
| 10 | D7 | output | Digital Data Output |
| 11 | D8 | output | Digital Data Output |
| 12 | D9 | output | Digital Data Output |
| 13 | DRVDD | power in | Digital Output Driver Supply |
| 14 | DRVSS | power in | Digital Output Driver Ground |
| 15 | DVSS | power in | Digital Ground |
| 16 | DATACLK | input | Digital Data Output Latch Clock |
| 17 | DVDD1 | power in | Digital Supply |
| 18 | HD | input | Horizontal Drive |
| 19 | PBLK | input | Preblanking Clock Input |
| 20 | CLPOB | input | Black Level Clamp Clock Input |
| 21 | SHP | input | CDS Sampling Clock for CCD's Reference Level |
| 22 | SHD | input | CDS Sampling Clock for CCD's Data Level |
| 23 | CLPDM | input | Input Clamp Clock Input |
| 24 | VD | input | Vertical Drive |
| 25 | AVSS | power in | Analog Ground |
| 26 | AVSS | power in | Analog Ground |
| 27 | AVDD1 | power in | Analog Supply |
| 28 | BYP1 | passive | Internal Bias Level Decoupling |
| 29 | BYP2 | passive | Internal Bias Level Decoupling |
| 30 | CCDIN | input | Analog Input for CCD Signal |
| 31 | NC | no connect | Internally Not Connected |
| 32 | BYP4 | passive | Internal Bias Level Decoupling |
| 33 | AVDD2 | power in | Analog Supply |
| 34 | AUX2IN | input | Analog Input |
| 35 | AVSS | power in | Analog Ground |
| 36 | AUX1IN | input | Analog Input |
| 37 | CML | passive | Internal Bias Level Decoupling |
| 38 | VRT | passive | A/D Converter Top Reference Voltage Decoupling |
| 39 | VRB | passive | A/D Converter Bottom Reference Voltage Decoupling |
| 40 | DVDD2 | power in | Digital Supply |
| 41 | DVSS | power in | Digital Ground |
| 42 | THREE-STATE | input | Digital Output Disable. Active High |
| 43 | NC | no connect | May be tied high or low. Do not leave floating. |
| 44 | STBY | input | Standby Mode, Active High |
| 45 | NC | no connect | Internally Not Connected |
| 46 | SL | input | Serial Digital Interface Load Pulse |
| 47 | SDATA | input | Serial Digital Interface Data |
| 48 | SCK | input | Serial Digital Interface Clock |
절대 최대 정격
| AVDD1, AVDD2 | 3.9V | max |
| AVSS | -0.3V | min |
| DVDD1, DVDD2 | 3.9V | max |
| DVSS | -0.3V | min |
| DRVDD | 3.9V | max |
| DRVSS | -0.3V | min |
| Junction Temperature | 150°C | max |
| Lead Temperature | 300°C | 10 sec |
권장 동작 조건
| Supply Voltage | 3V | typ |
열 특성
- theta ja
- 92
오더링 코드
- AJST
- LQFP package, -20°C to +85°C
유사 부품
이 부품을 사용한 Reference Design
0건제조사가 검증한 시스템 회로 + BOM + Gerber 자료. 데이터시트의 typical circuit 보다 한 단계 완제품에 가까움.