== PT100 range
  T=  -50 C  R=  80.3063 ohm  dR/dT=0.39713 ohm/C
  T=    0 C  R= 100.0000 ohm  dR/dT=0.39083 ohm/C
  T=   25 C  R= 109.7347 ohm  dR/dT=0.38794 ohm/C
  T=  100 C  R= 138.5055 ohm  dR/dT=0.37928 ohm/C
  T=  200 C  R= 175.8560 ohm  dR/dT=0.36773 ohm/C

== excitation / RTD dissipation
  I_max = 1.0320 mA ; P_RTD max = 0.1873 mW (limit 1 mW)

== compliance and PGA input range (worst case, IDAC at max)
  V(IDAC pin) = 1.9565 V  limit AVDD-0.6 = 2.5330 V  margin 0.576 V
  VIN max = 181.48 mV ; VAINP max = 1.8430 V <= 2.3478 V (margin 0.505) ; VAINN min = 1.5488 V >= 0.7852 V
  full scale VREF/G = 200.0 mV (at 1 mA) ; Rmax/RREF*G = 0.8793 of FS ; VREF = 1.600 V nominal, min 1.549 V (>=0.5 V and >1/3 AVDD=1.100 V)

== input filter
  f_diff = 7315 Hz ; f_cm = 57335 Hz ; tau_diff = 22.8 us ; 1 ppm settling = 0.316 ms
  definitions: f_diff includes the RTD (Rmax) and both 1.00 k resistors; f_cm includes the RTD, one 1.00 k and RREF in the source path; the filter alone (1.00 k / 1 nF) has its corner at 159 kHz
  f_ref = 6121 Hz (R15 1.00 k + RREF 1600 ohm source resistance, C18 10 nF)

== open-lead diagnostic (gain 4, 10 uA burn-out sources)
  measurement accepts R < 196.0 ohm (0.98 FS at gain 8, ratiometric, any IDAC current)
  largest healthy diagnostic reading (R up to 196 ohm, I_BO up to 20 uA [A]): 0.604 FS (rejection at 0.98 FS)
  80 ohm standard: shift 20.2..21.5 ohm-equivalent at 10 uA; 10.1..43.0 ohm over 5..20 uA [A]; accept window 9..50 ohm
  180 ohm standard: shift 21.1..22.5 ohm-equivalent at 10 uA; 10.6..45.1 ohm over 5..20 uA [A]; accept window 9..50 ohm
  R at OVERRANGE limit: shift 21.3..22.7 ohm-equivalent at 10 uA; 10.6..45.4 ohm over 5..20 uA [A]; accept window 9..50 ohm
  open sense lead: node <= 13.55 nF must move by <= FS = 413 mV: <= 1.12 ms at the assumed 5 uA minimum [A] (0.56 ms at 10 uA typical); diagnostic wait 2.0 ms, then the code saturates (rejection by saturation, not by the shift window)
  cable: 10 ohm x 2 nF = 20 ns (negligible)

== electronics error budget (after 2-point calibration at 25 C, board 0..50 C)
 -- excitation current nominal 1.000 mA
  T = 200 C  (R = 175.856 ohm, 0.3677 ohm/C)
    [G] RREF TCR, |0.2 typ + 1.8 max spread| = 2.0 ppm/C x 25 C (VSMP Table 1)                  23.91 mK
    [G] ADC gain drift, 2 ppm/C max (-40..85 C) x 25 C                                          23.91 mK
    [G] ADC offset drift, 200 nV/C max (G 1-8) x 25 C                                           13.60 mK
    [G] Absolute input current change, each sense line within +/-2 nA (PGA on, full input range): 2 x 4 nA x 1.011 k  21.99 mK
    [C] AVDD PSRR 90 dB min x AVDD change within the envelope 3.135..3.35 V (envelope conditional on the VF design value)  18.49 mK
    [C] INL after 2-point cal: <= 2 x 15 ppmFSR, FSR = 2 x Iex x RREF / G at this current (specified at VCM = AVDD/2)  32.63 mK
    [C] Clamp leakage change, 5 diodes (4 FORCE+, 1 FORCE_RTN) x 8.7 nA (interpolated 5 nA/25 C, 80 nA/150 C at 75 V)  20.80 mK
    [C] REFP0 input current change 15 nA (limit specified for REFP1/REFN1)                      11.66 mK
    [C] Differential input current residual, +/-1 nA x 1.011 k (specified at VCM = AVDD/2 only)   2.75 mK
    [U] calibration standards 20 ppm expanded uncertainty (k = 2), normal: 9.56 mK (sigma 4.78 mK)
    [N] noise, one 20 SPS sample (typical): 0.54 mK rms, 3.26 mK pp
    T= 200 C: [G] sum   83.4 mK ; complete linear sum  182.6 mK ; statistical k=2   71.8 mK
  T = 0 C  (R = 100.000 ohm, 0.3908 ohm/C)
    [G] RREF TCR, |0.2 typ + 1.8 max spread| = 2.0 ppm/C x 25 C (VSMP Table 1)                  12.79 mK
    [G] ADC gain drift, 2 ppm/C max (-40..85 C) x 25 C                                          12.79 mK
    [G] ADC offset drift, 200 nV/C max (G 1-8) x 25 C                                           12.79 mK
    [G] Absolute input current change, each sense line within +/-2 nA (PGA on, full input range): 2 x 4 nA x 1.011 k  20.69 mK
    [C] AVDD PSRR 90 dB min x AVDD change within the envelope 3.135..3.35 V (envelope conditional on the VF design value)  17.40 mK
    [C] INL after 2-point cal: <= 2 x 15 ppmFSR, FSR = 2 x Iex x RREF / G at this current (specified at VCM = AVDD/2)  30.70 mK
    [C] Clamp leakage change, 5 diodes (4 FORCE+, 1 FORCE_RTN) x 8.7 nA (interpolated 5 nA/25 C, 80 nA/150 C at 75 V)  11.13 mK
    [C] REFP0 input current change 15 nA (limit specified for REFP1/REFN1)                       6.24 mK
    [C] Differential input current residual, +/-1 nA x 1.011 k (specified at VCM = AVDD/2 only)   2.59 mK
    [U] calibration standards 20 ppm expanded uncertainty (k = 2), normal: 5.12 mK (sigma 2.56 mK)
    [N] noise, one 20 SPS sample (typical): 0.51 mK rms, 3.07 mK pp
    T=   0 C: [G] sum   59.1 mK ; complete linear sum  135.3 mK ; statistical k=2   56.0 mK
  T = -50 C  (R = 80.306 ohm, 0.3971 ohm/C)
    [G] RREF TCR, |0.2 typ + 1.8 max spread| = 2.0 ppm/C x 25 C (VSMP Table 1)                  10.11 mK
    [G] ADC gain drift, 2 ppm/C max (-40..85 C) x 25 C                                          10.11 mK
    [G] ADC offset drift, 200 nV/C max (G 1-8) x 25 C                                           12.59 mK
    [G] Absolute input current change, each sense line within +/-2 nA (PGA on, full input range): 2 x 4 nA x 1.011 k  20.37 mK
    [C] AVDD PSRR 90 dB min x AVDD change within the envelope 3.135..3.35 V (envelope conditional on the VF design value)  17.12 mK
    [C] INL after 2-point cal: <= 2 x 15 ppmFSR, FSR = 2 x Iex x RREF / G at this current (specified at VCM = AVDD/2)  30.22 mK
    [C] Clamp leakage change, 5 diodes (4 FORCE+, 1 FORCE_RTN) x 8.7 nA (interpolated 5 nA/25 C, 80 nA/150 C at 75 V)   8.80 mK
    [C] REFP0 input current change 15 nA (limit specified for REFP1/REFN1)                       4.93 mK
    [C] Differential input current residual, +/-1 nA x 1.011 k (specified at VCM = AVDD/2 only)   2.55 mK
    [U] calibration standards 20 ppm expanded uncertainty (k = 2), normal: 4.04 mK (sigma 2.02 mK)
    [N] noise, one 20 SPS sample (typical): 0.50 mK rms, 3.02 mK pp
    T= -50 C: [G] sum   53.2 mK ; complete linear sum  123.9 mK ; statistical k=2   53.0 mK
 -- excitation current lowest permitted 0.968 mA
    T= 200 C: [G] sum   84.6 mK ; complete linear sum  185.6 mK ; statistical k=2   72.8 mK
    T=   0 C: [G] sum   60.2 mK ; complete linear sum  137.8 mK ; statistical k=2   56.9 mK
    T= -50 C: [G] sum   54.3 mK ; complete linear sum  126.1 mK ; statistical k=2   53.8 mK
 -- excitation current highest permitted 1.032 mA
    T= 200 C: [G] sum   82.3 mK ; complete linear sum  179.7 mK ; statistical k=2   70.9 mK
    T=   0 C: [G] sum   58.0 mK ; complete linear sum  133.0 mK ; statistical k=2   55.3 mK
    T= -50 C: [G] sum   52.2 mK ; complete linear sum  121.7 mK ; statistical k=2   52.2 mK
  largest statistical estimate: 72.8 mK at 200 C with lowest permitted 0.968 mA excitation

== isolated supply (input N3/N4, output N1/N2, n = 1.23 +/- 2 %)
  VF design value 0.407 V (Fig 1 typical -40 C 0.367 V + 25 C max-typ spread 0.04 V) [C]; typical 0 C interpolation 0.306 V
  ripple bound: I 8.43 mA x half period 1.38 us / C_eff 8.63 uF = 1.35 mV
  Vin=4.75: VRECT max 3.941 V (TPS7A20 VIN max rec. 6.0 V) ; VRECT min 3.367 V (VF 0.407, drops 10.3 mV, ripple 1.3 mV)
  Vin=5.0: VRECT max 4.148 V (TPS7A20 VIN max rec. 6.0 V) ; VRECT min 3.566 V (VF 0.407, drops 10.6 mV, ripple 1.3 mV)
  Vin=5.25: VRECT max 4.355 V (TPS7A20 VIN max rec. 6.0 V) ; VRECT min 3.765 V (VF 0.407, drops 11.0 mV, ripple 1.3 mV)
  TPS7A20 VDO definition: VIN >= 0.95 x 3.3 + 0.145 = 3.280 V keeps VOUT >= 3.135 V at 300 mA (load here <= 8.4 mA, monotonic in load per Fig 5-27/5-28 [C])
  VRECT min 3.358 V -> margin 0.078 V ; spec accuracy (+/-1.5 %) needs VIN >= 3.6 V: NOT guaranteed at low line
  AVDD required: IDAC compliance and PGA range 2.628 V; device recommended minimum 2.700 V -> requirement 2.700 V ; supported floor 3.133 V [C, rests on the VF design value] -> margin 0.433 V
  combined VF + VDO budget that still meets the ADC requirement: 1.065 V
  rectifier reverse voltage <= 2 x 4.36 = 8.71 V (PMEG VR 40 V) ; SN6505 drain off-voltage 2 x 5.25 = 10.5 V (abs max 16 V)
  volt-second on driven half-winding N3: 5.25 V / (2 x 363 kHz) = 7.23 Vus (N1 rating 11 Vus; N3 has 1.23x the turns of N1 -> 13.5 Vus, derived)
  I(3V3_ISO) max 8.43 mA ; P(rectifier out) <= 36.7 mW ; assumed efficiency 50% -> I_in(4.75 V) <= 15.5 mA + SN6505B IQ 2.3 mA
  I(3V3_HOST) max 8.81 mA (ISO7741 ICC1 worst DC row 6.8 mA >= 10 Mbps row 5.2 mA) ; total +5V_IN steady state ~ 26.6 mA (+ TVS leakage <= 0.4 mA)
  LDO dissipation: host 17.2 mW, iso 8.9 mW
  startup ESTIMATE (average charging, max-tolerance C): rectifier 22.1 uF, behind U3 13.6 uF (SN6505B tSS test load 40 uF)
    tSS=1.00 ms (SN6505B tSS: MIN 1, NOM 4.25, MAX 8 ms): average secondary ~141 mA -> primary ~115 mA; peak NOT bounded by the documents
    tSS=4.25 ms (SN6505B tSS: MIN 1, NOM 4.25, MAX 8 ms): average secondary ~68 mA -> primary ~55 mA; peak NOT bounded by the documents

== timing (worst case oscillator -1.5 %)
  20 SPS LL single-shot incl. 14 tMOD delay: 57.420 ms ; 400 SPS: 2.752 ms
  per channel: main 58.83 ms + open-lead check 5.19 ms = 64.02 ms
  monitor slot 4.24 ms ; scan cycle work 260.3 ms ; schedule period 300 ms ; margin to 400 ms 139.7 ms
  reverse RC: VOH 2.835 V -> 2.707 V at the host (47 k pull-down); to VIH 2.52 V takes 121.8 ns incl. tr

== SPI read path (worst case)
  forward RC 23.2 ns + isolator 18.5 + tp(SCDO) 30 + isolator 18.5 + R9 RC 121.8 + host setup 20 = 232.0 ns
  SCLK 2.0 MHz, shortest high phase (40 % duty) 200 ns -> margin -32 ns
  SCLK 1.5 MHz, shortest high phase (40 % duty) 267 ns -> margin +35 ns
  SCLK 1.0 MHz, shortest high phase (40 % duty) 400 ns -> margin +168 ns
  DOUT_ISO pull-up recovery: tau = 2.02 us; to 0.7 x VCC (1.2 tau) 2.42 us; idle-check wait 50 us = 25 tau
